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AES–XTS Encryption Storage IP Core

The IntelliProp IPC-BL120A-ZM is an AES-XTS Encryption Core supporting 128 or 256 bit encryption. The IPC-BL120A-ZM provides encryption/decryption based on a design principle known as substitution-permutation network (SP-network). An SP-network takes a block of the plaintext (clear data or non-encrypted data) and the key as inputs, and applies several alternating “rounds” or “layers” of substitution boxes and permutation boxes to produce the ciphertext (encrypted data). The IPC-BL120A-ZM is fully verified in pseudo random simulation.

AES Encryption Core with XTS Applications

  • Applications that require integration into the data path to provide encryption/decryption of data
  • Applications where high levels of encryption are required
  • Applications requiring FIPS-197 certified encryption/ decryption algorithms
  • Applications that require very high throughput and an encryption solution that has minimal impact on throughput

AES Encryption Core with XTS Features

  • Full Verilog core
  • Programmable number of pipeline states allows the user to balance area/bandwidth requirements.
  • 128 or 256 bit selectable AES encryption
  • The AES-XTS algorithm is FIPS-197 certified
  • The encode and decode channels are made to look and act like independent FIFOs for ease of integration. The control block has a register interface to be easily managed by a hardware state machine or controlled by a processor for operations such as key initialization, and TWEAK configuration and management.
  • This is a scalable design which allows for performance vs. area tradeoffs. The number of parallel pipelines can be configured to support high performance/high throughput applications as well as lower performance and/or resource limited applications.
  • The core has a simulation test bench and register initialization sequence to support rapid integration
  • Processor and RTL control interface
  • Independent Cipher/Inverse Cipher key management
  • Supports integer multiples of 16 byte Data Unit sizes
  • Verilog/VHDL support

 

Functional Description of AES Encryption Core with XTS

The IPC-BL120A-ZM is an IP core that is an encoder/decoder that allows the user to provide full disk encryption for their storage device. The IPC-BL120A-ZM supports AES-XTS with an option for 128 or 256 bit encryption levels and is capable of data throughput that support SATA 6Gb/s speed. The encryption algorithm on the IPC-BL120A-ZM is FIPS-197 certified.

aes encryption storage ip core with xts

 

Provided with Storage IP Core
Documentation:
Comprehensive User Documentation
Design File Formats:
Encrypted Verilog
Constraints Files:
Provided per FPGA
Verification:
ModelSim verification model
Instantiation Templates:
VHDL/Verilog
Reference Designs & Application Notes:
Synthesis and place and route scripts
Additional Items:
Simulation Script, Sample Vectors, Reference Design
Simulation Tool Used:
ModelSim (contact IntelliProp for latest versions supported)
Support:
The core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date.
Notes:
Other simulators are available. Please contact IntelliProp for more information.


Device Support
IntelliProp’s AES-XTS Encryption Core is available for integration into FPGA or ASIC devices.

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