asic design

ECC with BCH Algorithm Storage IP Core

IntelliProp’s IPC-BL119A-ZM is a highly configurable core that provides a method of extending an information block with extra bits to guard against the loss or corruption of data across noisy or unreliable communication channels. The ECC core uses the industry standard BCH class of error correcting codes.

Applications of the ECC with BCH Algorithm Core

  • Data storage devices (SATA, SAS, FLASH)
  • Compact DISC
  • Two dimensional bar codes
  • Satellite communications / telemetry
  • Radiowave signal recording
  • Wireless communications
  • High-speed modems such as ADSL, xDSL, etc…
  • Power line standards


Features of the ECC with BCH Algorithm Core

  • High bandwidth, low latency parallel encode and decode paths
  • Configurable number of encode blocks
  • Configurable number of decode blocks
  • Configurable code word length (K), up to 512 bytes
  • Configurable block size
  • Configurable 32, 64, 128, or 256 "FIFO" data interface
  • Parallelized encoder
  • Parallelized decoder for syndrome calculations
  • User selectable error correction values (T)
  • Quarantine RAM area allowing for 'on-the-side' firmware controlled extra correction capability allowing for single excessive block decode to be set aside and corrected by outside processor cycles.

 

Provided with Storage IP Core
Documentation:
Comprehensive User Documentation
Design File Formats:
Encrypted Verilog
Constraints Files:
Provided per FPGA
Verification:
ModelSim verification model
Instantiation Templates:
VHDL/Verilog
Reference Designs & Application Notes:
Synthesis and place and route scripts
Additional Items:
Simulation Script, Sample Vectors, Reference Design
Simulation Tool Used:
Contact IntelliProp for latest versions supported
Support:
The core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date.
Notes:
Other simulators are available. Please contact IntelliProp for more information.

 

FPGA Support:
IntelliProp’s ECC with BCH Algorithm Storage IP Core is available for integration into FPGA and ASIC devices

Call 303–774–0535 or e-mail a request for our ECC with BCH Algorithm IPC-BL119A-ZM datasheet or to schedule a demonstration.

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