asic design

NVMe Host Accelerator IP Core – IPC-NV164-HI

IntelliProp’s IPC-NV164-HI NVMe Host Accelerator IP Core provides a simplified, high-bandwidth interface to industry standard NVMe storage devices. 

The IntelliProp NVMe Host Accelerator IP Core provides a small footprint processor or RTL state-machine register interface for data movement between a user-defined data buffer and an NVMe target. Additionally, the NVMe Host Accelerator IP Core requires minimal knowledge of the PCIe and NVMe specification. The embedded Command Processor handles initialization of the NVMe Root Complex, building command submissions, parsing command completions, and initializing command queues.

NVMe Host Accelerator IP Core Applications

The IPC-NV164-HI is available for integration into FPGA or ASIC designs to provide an industry compliant NVMe interface. Supports 3rd party PCIe Root Complex IP cores:

  • Protocol-X to NVMe Bridge
  • NVMe to NVMe Bridge Systems
  • NVMe Fabric Accelerators
  • NVMe RAID Application
  • Embedded applications requiring non-volatile storage
     

NVMe Host Accelerator IP Core Features

  • Fully compliant to the NVM Express 1.2.1 industry specification
  • Compliant with 3rd party PCIe Root Complex IP cores
  • Automated initialization process with PCIe Hard Block
  • Automated command submission and completion
  • Scalable I/O queue depth
  • Support for 64k outstanding I/O commands
  • Scalable data buffer size up to 1GB
  • Processor or State Machine driven interface
  • Submission queue command context error prevention
  • Support for block sizes from 512 byte to 16kB
  • Application layer (command based) interface with Processor interface
  • Verilog support (VHDL wrappers only)

 


 

Provided with the NVMe Host Accelerator IP Core
Documentation:
Comprehensive User Documentation
Design File Formats:
Encrypted Verilog
Constraints Files:
Provided per FPGA
Verification:
ModelSim verification model
Instantiation Templates:
Verilog (VHDL wrappers available)
Reference Designs & Application Notes:
Synthesis and place and route scripts
Additional Items:
Reference Design
Simulation Tool Used:
ModelSim (Contact IntelliProp for latest versions supported)
Support:
The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date.
Notes:
Other simulators are available. Please contact IntelliProp for more information.

 

Functional Description

The IPC-NV164-HI NVMe Host Accelerator IP Core provides a simple firmware or RTL driven interface for data movement to and from an NVMe endpoint attached to a PCIe link. The interface to the IP core is designed to be driven by a User Logic state machine or processor. All command submission and completion queues are managed by the internal state machines. Users will write command submission context to the Command Registers and arm the Command Submission State Machine to send a command to the NVMe endpoint. Users will read command completion context from the Command Registers when command completions have been parsed by the Command Completion State Machine.

The NVMe Host Accelerator IP Core can be replicated within the user's application to communicate with multiple NVMe endpoints.

All data transfers occur through a user-defined, system-attached memory, such as an on-chip block RAM or off-chip DDR, connected to the PCIe Hard Block.
 

Click here to request the NVMe Host Accelerator IP Core (IPC-NV164-HI) datasheet...>
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