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sata host core certified

SATA Device ADCI Core - IPC-SA155A-DT

The IntelliProp IPC-SA155-DT is an industry standard Serial-ATA (SATA) device interface core that allows customers to build high speed storage devices. The protocol interface is compliant to the SATA 3.3 specification as defined by the Serial ATA International Organization (SATA-IO). The IPC-SA155-DT is fully verified using a coverage driven methodology in pseudo random simulation.

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Applications for the SATA Device ADCI IP Core include

The IPC-SA155-DT is available for integration into device ASIC or FPGA designs to provide an industry compliant SATA 1.5 Gb/s, SATA 3.0 Gb/s, or SATA 6.0 Gb/s interface.  The target applications for the IPC-SA155-DT include:

  • Internal connections to computer motherboards
  • E-SATA storage
  • HDD or SSD


IPC-SA155-DT Features

  • Application layer (command based) interface with Processor interface (ADCI)
  • Data Interface through FIFOs
  • Processor interface for register access
  • Supports either SerDes, PIPE, or SAPIS interface
  • Synchronous design for easy integration
  • Verilog/VHDL Support
  • Power Modes (partial/slumber)
  • Support for DEVSLP
  • Built in Self-Test


SATA Device ADCI Core
Comprehensive User Documentation
Design File Formats:
Encrypted Verilog
Constraints Files:
Provided per FPGA
ModelSim verification model, Testbench and Host Model included
Instantiation Templates:
Verilog (VHDL wrappers available)
Reference Designs & Application Notes:
Synthesis and place and route scripts
Additional Items:
Reference Design
Simulation Tool Used:
ModelSim (Contact IntelliProp for latest versions supported)
The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date.
Other simulators are available. Please contact IntelliProp for more information.


Functional Description

The IPC-SA155-DT is designed to be a SATA-compliant device application to send and receive Out of Band (OOB) signals, primitives and SATA Frame Information Structures (FIS). The SATA Device core interfaces to the system via a DMA engine for data movement and a memory mapped register set for control by the embedded processor. This allows for efficient data movement between a data buffer or cut-through FIFOs and the SATA Core. The reception of standard or vendor specific commands will interrupt the processor and allow for flexible command completion.


Click Here to Request the SATA Device ADCI Core (IPC-SA155-DT) datasheet...>
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